Devices having improved capacitance and methods of their fabrication

ABSTRACT

A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has first and second conductive plates and a dielectric is formed from the first conductive plate.

BACKGROUND

[0001] Although there have been attempts to deposit metal oxides, suchas TiO2 and SrTiO3, during semiconductor fabrication, thermal oxidationof metals in the fabrication of capacitors has been limited since aninitial oxide layer prohibits further diffusion during thermaloxidation. As a result the use of high dielectric constant oxidizedmetals has been limited in semiconductor capacitor fabrication. One suchmetal, titanium dioxide, has a dielectric constant 2-15 times greaterthan present semiconductor capacitor dielectrics such as siliconnitride, while titanates are 2-1000 times greater.

[0002] In the January 1996 issue of Material Research, Vol. 11, No. 1,an article entitled ELECTROCHEMICAL SYNTHESIS OF BARIUM TITANATE THINFILMS, R. R. Bacsa et al. describes the synthesizing of polycrystallinefilms of barium titanate on titanium substrates by the galvanostaticanodization of titanium to form a material which has a dielectricconstant of 200.

SUMMARY OF THE INVENTION

[0003] The invention includes new capacitor structures and dielectricsand methods for forming such capacitors and dielectrics.

[0004] In one exemplary embodiment the capacitor of the invention isformed by a process using only two deposition steps. The capacitor hasfirst and second conductive plates and a dielectric is formed from thefirst conductive plate.

[0005] In one exemplary process in accordance with the present inventiona metal layer is deposited and at least partially oxidized in anelectrolytic solution. The metal oxide formed during this oxidationforms the dielectric of the capacitor. Portions not oxidized may form atleast a portion of a capacitor plate.

[0006] In one exemplary implementation in accordance with the presentinvention, a metal layer is deposited to overlie a first capacitor platefabricated on a semiconductor wafer. The wafer is placed in anelectrolyte conducive to forming an oxide with the metal. A potential isapplied across the electrolyte and the metal, and at least a portion ofthe metal oxidizes. In a preferred embodiment the metal is titanium andtitanium dioxide is formed during the electrochemical reaction. Thecapacitor fabrication is completed with the formation of a secondcapacitor plate overlying the oxidized metal layer. The oxidized metallayer functions as the dielectric of the capacitor and has a highdielectric constant.

BRIEF DESCRIPTION OF THE FIGURES

[0007]FIG. 1 is a cross section of a semiconductor wafer following theformation of a silicon dioxide layer and the masking thereof.

[0008]FIG. 2 is the cross section of FIG. 1 following an etch of thesilicon dioxide layer and following a deposition and etch ofpolysilicon.

[0009]FIG. 3 is the cross section shown in FIG. 2 following a depositionof titanium.

[0010]FIG. 4 is the cross section shown in FIG. 3 when placed in anapparatus configured to perform electrochemical oxidation.

[0011]FIG. 5 is the cross section shown in FIG. 4 following theoxidation of the titanium layer.

[0012]FIG. 6 is the cross section shown in FIG. 5 following thedeposition and masking of a conductive layer.

[0013]FIG. 7 is the cross section shown in FIG. 6 following the finalcapacitor formation.

[0014]FIG. 8A is the cross section of the semiconductor wafer shown inFIG. 1 following an etch of the silicon dioxide layer and a deposit of afirst metal layer.

[0015]FIG. 8B is the cross section of the semiconductor wafer shown inFIG. 1 following an etch of the silicon dioxide layer and a deposit andplanarization of a first metal layer.

[0016]FIG. 9A is the cross section shown in FIG. 8A following theelectrochemical oxidation of the first metal layer and a deposit of asecond metal layer.

[0017]FIG. 9B is the cross section shown in FIG. 8B following theplanarization and electrochemical oxidation of the first metal layer andfollowing a deposit and planarization of a second metal layer.

[0018]FIG. 10A is the cross section shown in FIG. 9A following anelectrochemical oxidation of the second metal layer.

[0019]FIG. 10B is the cross section shown in FIG. 9B following aelectrochemical oxidation of the second metal layer.

[0020]FIG. 11A is the cross section shown in FIG 10A following theformation of a capacitor plate and the masking thereof.

[0021]FIG. 11B is the cross section shown in FIG 10B following theformation of a capacitor plate and the masking thereof.

[0022]FIG. 12A is the cross section shown in FIG. 11A following an etchand showing one capacitor of the invention.

[0023]FIG. 12B is the cross section shown in FIG. 11B following an etchand showing one capacitor of the invention.

[0024]FIG. 13 is a block schematic of a memory system of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] FIGS. 1-7 depict cross sectionally a semiconductor wafer 1following the process steps of a first embodiment used in fabricatingthe wafer 1. In FIG. 1 field oxide regions 2 and wordlines 3 have beenformed overlying a substrate 4 using conventional semiconductor processmethods. Following the wordline formation a thick layer of silicondioxide 5 is deposited to a thickness approximately equal to 5000angstroms and then planarized. The silicon dioxide 5 is masked to definefuture capacitor substrate contact regions with mask layer 15.

[0026] In FIG. 2 the silicon dioxide 5 is anisotropically dry etched toexpose the substrate 4 in the unmasked regions. Following the etch asubstantially conformal first conductive layer 25, preferably apolysilicon layer having a thickness of 200-400 angstroms, is depositedto overly the exposed substrate 4 and the silicon dioxide 5. Followingthe formation of the conductive layer 25 upper portions of the silicondioxide layer 5 are exposed by removing portions of the conductive layer25 using a spacer etch or using CMP (chemical mechanical planarization)following a resist deposit. The removal of portions of the conductivelayer 25 creates electrically isolated portions of the conductive layer25. The isolated portions of conductive layer 25 are first capacitorplates of the capacitor of the invention. Conventional methods fordepositing the conductive layer 25 include CVD (chemical vapordeposition), PVD (pressure vapor deposition) and electroless deposition.In an alternate embodiment a metal layer is deposited by a conventionalmethod and functions as the first conductive layer 25

[0027] Following the deposition and isolation of portions of the firstconductive layer 25 a conformal metal layer 30 is deposited by chemicalvapor deposition to overly the first conductive layer 25 and exposedportions of silicon dioxide layer 5, see FIG. 3. In a preferredembodiment the conformal metal layer 30 is titanium having a thicknessof approximately 16-100 angstrom. Although in this embodiment titaniumis preferred other metals may be used such as copper, gold, tungsten,and nickel. In a case where metal is used as the first conductive layer25 it may be necessary to form diffusion barrier layer or an oxidationresistant layer or both interposed between the first conductive layer 25and the metal layers 30. Thus, it should be noted that the firstconductive layer 25 may actually be comprised of more than one material.For example in a ministack application a conductive plug and furtherconductive layers overlying the conductive plug may form the firstconductive layer.

[0028] In FIG. 4 the wafer 1 is placed in electrolytic solution 34conducive to oxidizing the metal layer 30 when a potential is appliedacross the electrolytic solution 34 and the metal layer 30. Theelectrolytic solution 34 contacts the metal layer 30. In the preferredembodiment the electrolytic solution 34 is water, such as one part NH4OHfor 10 parts water or 0.1 Mole HCLO4. However, a basic or acidicsolution could also be used. A potentiostat 36 consists of a firstelectrode 40, known as a counter electrode, and a second electrode 45,known as a reference electrode. Both the first 40 and second 45electrodes are emersed in the electrolytic solution 34. The potentiostat36 also provides a third electrode 46, known as the working electrode,which is connected to the substrate 4. The substrate 4 is in electricalcommunication with the metal layer 30. The potentiostat 36 is a standarddevice, one of which is a PAR available from E.G.& G. of Princeton, N.J.The preferred reference electrode is an SCE (saturated calomelelectrode). The potentiostat 36 monitors the current flowing between thefirst and third electrodes 40 and 46. The potentiostat controls thepotential between the second and third electrodes 45 and 46. Preferably,the potential is in the range of −2.0 volts to 5 volts (i.e. SCEreference electrode) for 5-120 sec depending on the desired thickness ofthe dielectric. The current is measured between electrodes 40 and 46 andis controlled by varying the potential between the second and thirdelectrodes 45 and 46 to obtain the desired current. The potentiostatallows the potential to be adjusted within a range of potentialsconducive to the oxidizing of titanium. The oxidation reactionsimultaneously oxidizes the metal layer 30 across the entire wafersurface.

[0029] Although in the preferred embodiment a three electrodepotentiostat controls the electrochemical oxidation process, a twoelectrode rheostat control device may also be used. However, theoxidation is less controllable using the two electrode rheostat. Whenusing the rheostat the second electrode 45 is eliminated and theelectrochemical reaction changes the counter electrode chemistry. Whenthis happens the potential changes. Thus the oxidation of the metallayer 30 is uncontrolled. In the three electrode preferred embodimentthe existence of the reference electrode provides better control of theoxidation process.

[0030] In the first embodiment substantially all of the metal layer 30is oxidized during the electrolytic process to form a metal oxide 35,titanium dioxide in the preferred embodiment, see FIG. 5. The titaniumdioxide has a high dielectric constant. Preferably, the thickness of themetal oxide ranges between 10-1000 Angstroms and the dielectric constantis between 86 and 170.

[0031] Following the oxidation step the metal oxide is chemicallymechanically planarized and a second conductive layer 55 is deposited tooverlie the metal silicon dioxide layer 5, the silicon oxide 50 and themetal oxide 35, see FIG. 6. The second conductive layer 55 is createdusing conventional methods such as CVD, PVD, or electroless deposition.In the preferred embodiment the conductive layer 55 is polysiliconalthough metal may be used instead of polysilicon, and more than onematerial may be used to form conductive layer 55. A mask 60 is thenformed to define the future capacitor structures.

[0032] In FIG. 7 the conductive layer 55 has been etched in unmaskedregions to complete the capacitor structures 65. The capacitors 65 madeby the method of the invention comprises a first capacitor plate whichis first conductive layer 25, a second capacitor plate which is thesecond conductive layer 55, and a dielectric which is the metal oxide35.

[0033] In an alternate embodiment it is only necessary to oxidize aportion of the metal layer 30 to create a metal/metal oxide layer, or inthe preferred embodiment a titanium/titanium dioxide layer. In this casethe unoxidized metal layer 30 and the polysilicon layer 25 form thefirst capacitor plate while the thin layer of titanium oxide forms thedielectric.

[0034] In a still further alternate embodiment multiple layers of metalare deposited and at least a portion of each metal layer iselectrochemically oxidized prior to the deposition of a subsequent metallayer. In this case the dielectric comprises alternate layers of oxideand metal. In this embodiment the second conductive layer 55 isdeposited on the last metal oxide created.

[0035] In a second embodiment of the invention, shown in FIGS. 8A-12B, afirst metal layer 75, such as titanium, is sputter deposited to overlythe silicon dioxide layer 5 and to contact exposed portions of substrate4 following the etch of the silicon dioxide layer 5 shown in FIG. 1. Thewafer 1 is then placed in an electrolytic solution of acidic water. Acurrent flows in the electrolytic solution in response to a potentialapplied across the electrolytic solution. The current is controlled witha potentiostat in order to control the oxidation of the metal layer. Bycontrolling the oxidation it is possible to oxidize only a top portionof the first metal layer 75 to form a first metal oxide 80, see FIG. 9A.

[0036] Alternately the metal layer 75 is planarized to expose thesilicon dioxide prior to oxidation and formation of the first metaloxide 80, see FIGS. 8B and 9B.

[0037] Following the first oxidation a second metal layer 85, FIG. 9A,is sputter deposited to overlie the first metal oxide 80. Again thewafer 1 is placed in the electrolytic solution and an upper portion ofthe second metal layer 85 is oxidized to form a second metal oxide 90,see FIGS. 10A and 10B.

[0038] In the alternate embodiment, shown in FIGS. 9B and 10B, thesecond metal layer 85 has been planarized to expose the silicon dioxideprior to oxidation.

[0039] Following the oxidation of the second metal layer 85 a thirdmetal layer 95 is sputter deposited to overly the second metal oxidelayer 90, and capacitors are defined by a mask 100, see FIGS. 11A and11B.

[0040] Exposed first, second and third metal layers 75, 85, and 95 andexposed first and second metal oxide layers 80 and 90 are etched to formthe capacitors 105 of the invention, see FIGS. 12A and 12B. First andthird metal layers 75 and 95 form first and second capacitor plates ofthe capacitors 105, and the first and second metal oxide layers 80 and90 and second metal layer 85 form the dielectric of the capacitors 105.In a preferred embodiment the first, second, and third metal layers 75,85, and 95 are titanium. Therefore in the preferred embodiment the metaloxide layers 80 and 90 are titanium dioxide. It is also possible to useonly one or to use more than the number of metal/metal oxide layersdescribed above as the dielectric layer, or it is possible to oxidize anentire metal layer if it is not the first or last metal layer deposited.

[0041] In further conceived embodiments the metal layer 30 (in thisembodiment titanium) may be alloyed with a material, such as Strontium.In this case SrTiO3 is formed during the oxidation performed by themethod of the invention. Other titanates may also be formed depending onthe alloy used in combination with titanium. For Example, Ba or Pb maybe combined with Ti to form BaTiO3 and PbTiO3, respectively, duringoxidation. The process also works for TiO3⁻² complexes. In a stillfurther embodiment the metal layer 30 (in this embodiment titanium) maybe oxidized in a supersaturated Sr⁺² solution such as Sr(OH)2 to formSrTrO3, in a preferred embodiment.

[0042] The capacitors 65 and 105 shown in FIGS. 7 and 12(A&B)respectively are typically used in a monolithic memory device 110, suchas a dynamic random access memory device, as shown in FIG. 13. Themonolithic memory device 110 and a processor 115 form part of a memorysystem 120. The processor 115 is typically used to generate externalcontrol signals which accesses the monolithic memory device 110 eitherdirectly or through a memory controller.

[0043] It will be evident to one skilled in the art that many differentcombinations of materials, deposits and etch steps may be used tofabricate the capacitor and dielectric of the invention withoutdeparting from the spirit and scope of the invention as claimed. Themethod for forming the dielectric of the invention is equally applicableto any type of capacitor structure, such as trench, container, andstacked and ministacked or variations thereof. The following patents:U.S. Pat. No. 5,438,011 (Blalock et al.), U.S. Pat. No. 5,097,381 (Vo),U.S. Pat. No. 5,155,057 (Dennison et al.), U.S. Pat. No. 5,321,649 (Leeet al.), U.S. Pat. No. 5,196,364 (Fazan et al.), U.S. Pat. No. 5,381,302(Sandhu et al.), U.S. Pat. No. 5,392,189 (Fazan et al.), U.S. Pat. No.5,082,797 (Chan et al.), U.S. Pat. No. 5,134,085 (Gilgen et al.), U.S.Pat. No. 5,354,705 (Mathews et al.), U.S. Pat. No. 5,049,517 (Liu etal.), U.S. Pat. No. 5,053,351 (Fazan et al.), U.S. Pat. No. 5,061,650(Dennison et al.), U.S. Pat. No. 5,168,073 (Gonzalez et al.). U.S. Pat.No. 5,192,703 (Lee et al), U.S. Pat. No. 5,262,343 (Rhodes et al.), U.S.Pat. No. 5,234,856 (Gonzalez), and U.S. Pat. No. 5,416,348 (Jeng)pertaining to the fabrication of capacitors are herein incorporated byreference. Therefore the invention is only limited by the claims.

What is claimed is:
 1. A method for forming a capacitor dielectric on asemiconductor substrate assembly, comprising the following steps:providing said semiconductor substrate assembly; forming a metalcapacitor plate on said substrate assembly; and oxidizing a portion ofsaid metal capacitor plate to form a dielectric.
 2. A method for forminga capacitor, comprising the following steps: forming a metal capacitorplate on a substrate assembly; and forming a dielectric from a portionof the capacitor plate.
 3. The method as specified in claim 2 , furthercomprising the step of forming a further capacitor plate overlying thedielectric.
 4. The method as specified in claim 3 , wherein said step offorming the capacitor plate comprises depositing a material to form thecapacitor plate.
 5. The method as specified in claim 2 , furthercomprising oxidizing the portion of the capacitor plate to form thedielectric.
 6. The method as specified in claim 2 , further comprisingthe step of applying a potential across an electrolytic solution and themetal capacitor plate to oxidize said metal capacitor plate.
 7. A methodfor forming a dielectric layer, comprising the following steps: forminga metal layer overlying a starting substrate; and applying a potentialacross an electrolytic solution and the metal layer to form thedielectric.
 8. The method as specified in claim 7 , further comprisingthe step of oxidizing at least a portion of the metal layer to form anoxidized layer in response to said step of applying, said oxidized layerforming at least a portion of the dielectric layer.
 9. A method forforming a dielectric layer, comprising the following steps: forming ametal layer overlying a starting substrate; applying a potential acrossthe metal layer; and oxidizing at least a portion of the metal layer toform an oxidized layer in response to said step of applying, saidoxidized layer forming at least a portion of the dielectric layer.
 10. Amethod for fabricating a wafer, comprising the following steps: forminga metal layer overlying a starting substrate; and applying a potentialacross an electrolytic solution and the metal layer.
 11. A method offabricating a wafer, comprising the following steps: forming a metallayer overlying a starting substrate; contacting the metal layer with anelectrolytic solution; applying a potential across the electrolyticsolution and the metal layer; and oxidizing at least a portion of themetal layer in response to said step of applying to form an oxidizedlayer.
 12. The method specified in claim 11 , further comprising forminga capacitor plate overlying the starting substrate prior to said step offorming the metal layer, said metal layer overlying said capacitorplate.
 13. The method as specified in claim 11 , further comprisingforming a capacitor plate overlying the oxidized layer.
 14. The methodas specified in claim 11 , wherein a non-oxidized portion of the metallayer forms at least a portion of a capacitor plate.
 15. The method asspecified in claim 11 , wherein said step of applying further comprises:connecting a first electrode in contact with the electrolytic solutionto a first terminal of a potential source; and connecting the startingsubstrate to a second terminal of the potential source.
 16. The methodas specified in claim 15 , further comprising: positioning a secondelectrode to contact the electrolytic solution; and connecting thesecond electrode to the potential source.
 17. The method as specified inclaim 11 , further comprising the step of adjusting the potential acrossthe electrolytic solution to control the oxidation of the metal layer.18. The method as specified in claim 17 , further comprising: monitoringa current in the electrolytic solution; and adjusting the potential ofthe electrolytic solution to maintain a desired amount of the current.19. A capacitor, comprising: a first conductive plate; a secondconductive plate; and a dielectric interposed between said first andsecond conductive plates, wherein said dielectric is an oxide of amaterial of the first conductive plate.
 20. A memory system, comprising:a monolithic memory device, comprising a capacitor, wherein thecapacitor comprises: a first conductive plate; a second conductiveplate; and a dielectric interposed between said first and secondconductive plates, wherein said dielectric is an oxide of a material ofthe first conductive plate; and a processor configured to access themonolithic memory device.
 21. A method for forming a dielectric layer,comprising the following steps: forming a metal layer overlying astarting substrate; contacting the metal layer with an electrolyticsolution; applying a potential across the electrolytic solution and themetal layer; and oxidizing at least a portion of the metal layer to forman oxidized layer in response to said step of applying, said oxidizedlayer forming at least a portion of the dielectric layer.
 22. The methodas specified in claim 21 , further comprising the step of forming acapacitor plate overlying the starting substrate prior to said step offorming the metal layer.
 23. The method as specified in claim 21 ,further comprising the step of forming a capacitor plate overlying theoxidized layer.
 24. The method as specified in claim 21 , wherein a nonoxidized portion of the metal layer forms a capacitor plate.
 25. Themethod as specified in claim 21 , wherein said step of applyingcomprises the following steps: connecting a first electrode in contactwith a surface of the electrolytic solution to a first terminal of apotential source; and connecting the starting substrate to a secondterminal of the potential source.
 26. The method as specified in claim25 , further comprising the following steps: positioning a thirdelectrode to contact the electrolytic solution; and connecting the thirdelectrode to a third terminal of the potential source.
 27. The method asspecified in claim 21 , wherein said step of applying comprises the stepof adjusting the potential across the electrolytic solution to controlthe oxidation of the metal layer.
 28. The method as specified in claim21 , further comprising the following steps: monitoring a current in theelectrolytic solution; and adjusting the potential of the electrolyticsolution to maintain a desired amount of the current.
 29. A method forforming a capacitor, comprising the following steps: forming a firstelectrically conductive layer; forming a metal layer overlying the firstelectrically conductive layer; contacting the metal layer with anelectrolytic solution; applying a potential across the electrolyticsolution and the metal layer; and oxidizing at least a portion of themetal layer to form an oxidized layer in response to said step ofapplying, said oxidized layer forming at least a portion of a dielectriclayer of the capacitor, the electrically conductive layer forming alower capacitor plate.
 30. The method as specified in claim 29 , furthercomprising forming a further electrically conductive layer overlying thedielectric layer to form an upper capacitor plate.
 31. A method forforming a capacitor dielectric layer, comprising the following steps:forming a metal layer overlying at least a portion of a startingsubstrate; contacting the metal layer with an electrolytic solution;applying a potential across the electrolytic solution and the metallayer; conducting current in the electrolytic solution in response tosaid step of applying; and oxidizing at least a portion of the metallayer to form a metal oxide in response to said step of conductingcurrent, the metal oxide forming at least a portion of the capacitordielectric layer.
 32. A method for forming a capacitor, comprising thefollowing steps: forming a metal layer in contact with a startingsubstrate; contacting the metal layer with an electrolytic solution;applying a potential across the electrolytic solution and the metallayer; conducting current in the electrolytic solution in response tosaid step of applying; and oxidizing a portion of the metal layer toform a metal oxide in response to said step of conducting current, themetal oxide being the capacitor dielectric, an unoxidized portion of themetal layer being a first capacitor plate.
 33. The method as specifiedin claim 32 , further comprising the step of forming a second capacitorplate overlying the capacitor dielectric.
 34. The method as specified inclaim 32 , wherein the metal layer is an initial metal layer and whereinthe electrolytic solution is an initial electrolytic solution andwherein the metal oxide is an initial metal oxide, and furthercomprising the following steps: forming a further metal layer to overlythe initial metal oxide; contacting the further metal layer with afurther electrolytic solution; applying a potential across the furtherelectrolytic solution and the further metal layer, conducting current inthe further electrolytic solution in response to said step of applying apotential across the further electrolytic solution; and oxidizing, inresponse to said step of conducting current, at least a portion of thefurther metal layer to form a further metal oxide, the further metaloxide forming a further portion of the capacitor dielectric.
 35. Themethod as specified in claim 34 , further comprising the step of forminga second capacitor plate overlying the capacitor dielectric.
 36. Themethod as specified in claim 34 , wherein the further electrolyticsolution and the initial electrolytic solution are the same solution.37. A method for forming a capacitor, comprising the following steps:forming an insulative layer overlying a substrate; masking theinsulative layer to define a region in which to fabricate the capacitor;removing the insulative layer in an unmasked region to expose thesubstrate; depositing a polysilicon layer overlying the insulative layerand the substrate and contacting the substrate; removing portions of thepolysilicon layer to expose the insulative layer; chemical vapordepositing a metal layer to overly the polysilicon layer and theinsulative layer; contacting the metal layer with an electrolyticsolution; applying an electrical potential to the electrolytic solutionand the metal layer; and oxidizing, in response to said step ofapplying, at least a portion of the metal layer to form a metal oxide tofunction as a dielectric layer.
 38. The method as specified in claim 37, further comprising forming a conductive layer overlying the metaloxide layer.
 39. A dielectric layer formed by the process, comprising:forming a metal layer overlying a starting substrate; contacting themetal layer with an electrolytic solution; applying a potential acrossthe electrolytic solution and the metal layer; and oxidizing at least aportion of the metal layer to form an oxidized layer in response to saidstep of applying, said oxidized layer forming at least a portion of thedielectric layer.
 40. The dielectric layer as specified in claim 39 ,further comprising forming a capacitor plate overlying the startingsubstrate prior to said step of forming the metal layer, said metallayer overlying said capacitor plate.
 41. The dielectric layer asspecified in claim 39 , wherein a non oxidized portion of the metallayer forms at least a portion of a capacitor plate.
 42. The dielectriclayer as specified in claim 39 , further comprising: connecting a firstelectrode in contact with the electrolytic solution to a first terminalof a potential source; and connecting the starting substrate to a secondterminal of the potential source.
 43. The dielectric layer as specifiedin claim 42 , further comprising: positioning a second electrode tocontact the electrolytic solution; and connecting the second electrodeto the potential source.
 44. The dielectric layer as specified in claim39 , further comprising the step of adjusting the potential across theelectrolytic solution to control the oxidation of the metal layer. 45.The dielectric layer as specified in claim 39 , further comprising:monitoring a current in the electrolytic solution; and adjusting thepotential of the electrolytic solution to maintain a desired amount ofthe current.
 46. A capacitor formed by a process, comprising: forming afirst capacitor plate; forming a metal layer overlying the firstcapacitor plate; contacting the metal layer with an electrolyticsolution; applying a potential across the electrolytic solution and themetal layer; and oxidizing at least a portion of the metal layer to forman oxidized layer in response to said step of applying, said oxidizedlayer forming at least a portion of a dielectric layer of the capacitor.47. The capacitor as specified in claim 46 , further comprising forminga conductive layer overlying the oxidized metal layer to form a secondcapacitor plate.
 48. A capacitor formed by a process. comprising:forming an insulative layer overlying a substrate; masking theinsulative layer to define a region in which to fabricate the capacitor;removing the insulative layer in an unmasked region to expose thesubstrate; depositing a polysilicon layer overlying the insulative layerand the substrate and contacting the substrate; removing portions of thepolysilicon layer to expose an upper surface of the insulative layer;depositing a metal layer to overly the polysilicon layer; contacting themetal layer with an electrolytic solution; applying an electricalpotential to the electrolytic solution and the metal layer; oxidizing,in response to said step of applying, at least a portion of the metallayer to form a metal oxide to function as a dielectric layer; andforming an electrically conductive layer overlying the metal oxide. 49.The capacitor as specified in claim 48 , further comprising forming aconductive layer overlying the metal oxide.
 50. A method of forming acapacitor comprising only two deposition steps.
 51. The method asspecified in claim 50 , further comprising: forming a first capacitorelectrode during a first deposition step; and forming a second capacitorelectrode during a second deposition step.
 52. The method as specifiedin claim 51 , further comprising forming a dielectric layer from saidfirst capacitor electrode.
 53. A capacitor comprising: a first capacitorelectrode; a dielectric layer formed from said first capacitorelectrode; and a second capacitor electrode.